Real-time attestation of cryptoprocessors lacking timers and counters

ABSTRACT

The present technology discloses methods and systems for receiving a security profile request from an integrity verifier, the request including a nonce; requesting, from a trusted platform module, a new nonce, wherein the new nonce is generated at least in part by the nonce and a current timestamp from a clock in the trusted platform module; receiving, from the trusted platform module, the new nonce; requesting, from a cryptoprocessor, a set of platform configuration registers; receiving, from the cryptoprocessor, the set of platform configuration registers; and sending a response to the integrity verifier, the response including the new nonce and the set of platform configuration registers to verify a security status of the trusted platform module and the cryptoprocessor.

TECHNICAL FIELD

The present disclosure generally relates to the field of computer networking, and more particularly to assessing reliability and trustworthiness of devices operating within a network.

BACKGROUND

Devices in today's networks require validation to ensure that they have not been compromised by a networking adversary. One common tool used to ensure up-to-date device measurements when validating device integrity involves preventing “replay attacks,” wherein out-of-date device measurements are sent by an adversary masquerading as up-to-date device measurements. However, not all device cryptoprocessors possess an internal clock, whose timestamps are crucial for preventing replay attacks.

BRIEF DESCRIPTION OF THE FIGURES

To provide a more complete understanding of the present disclosure and features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, in which:

FIGS. 1 through 3 illustrate example networking environments in accordance with some examples;

FIG. 4 illustrates an example of a controller orchestrated attestation-based routing, in accordance with some examples;

FIG. 5 illustrates an example system in accordance with some aspects of the present technology;

FIG. 6 illustrates an example method in accordance with some aspects of the present technology;

FIG. 7 illustrates an example network device in accordance with some examples; and

FIG. 8 illustrates an example computing device architecture in accordance with some examples.

DETAILED DESCRIPTION

Various embodiments of the disclosure are discussed in detail below. While specific implementations are discussed, it should be understood that this is done for illustration purposes only. A person skilled in the relevant art will recognize that other components and configurations may be used without parting from the spirit and scope of the disclosure. Thus, the following description and drawings are illustrative and are not to be construed as limiting. Numerous specific details are described to provide a thorough understanding of the disclosure. However, in certain instances, well-known or conventional details are not described in order to avoid obscuring the description. References to one or an embodiment in the present disclosure can be references to the same embodiment or any embodiment; and, such references mean at least one of the embodiments.

Reference to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others.

The terms used in this specification generally have their ordinary meanings in the art, within the context of the disclosure, and in the specific context where each term is used. Alternative language and synonyms may be used for any one or more of the terms discussed herein, and no special significance should be placed upon whether or not a term is elaborated or discussed herein. In some cases, synonyms for certain terms are provided. A recital of one or more synonyms does not exclude the use of other synonyms. The use of examples anywhere in this specification including examples of any terms discussed herein is illustrative only, and is not intended to further limit the scope and meaning of the disclosure or of any example term. Likewise, the disclosure is not limited to various embodiments given in this specification.

Without intent to limit the scope of the disclosure, examples of instruments, apparatus, methods and their related results according to the embodiments of the present disclosure are given below. Note that titles or subtitles may be used in the examples for convenience of a reader, which in no way should limit the scope of the disclosure. Unless otherwise defined, technical and scientific terms used herein have the meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. In the case of conflict, the present document, including definitions will control.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or can be learned by practice of the herein disclosed principles. The features and advantages of the disclosure can be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other features of the disclosure will become more fully apparent from the following description and appended claims, or can be learned by the practice of the principles set forth herein.

Overview

The disclosed technology presents a solution for preventing replay attacks on cryptoprocessors lacking internal clocks. The solution details methods and systems for creating a unique, time-dependent nonce that can be created outside a cryptoprocessor and used to request device integrity measurements. These unique, time-dependent nonces thus allow cryptoprocessor attestation to occur despite the cryptoprocessor lacking an internal clock.

In one aspect, a method includes receiving a security profile request from an integrity verifier, the request including a nonce; requesting, from a trusted platform module, a new nonce, wherein the new nonce is generated at least in part by the nonce and a current timestamp from a clock in the trusted platform module; receiving, from the trusted platform module, the new nonce; requesting, from a cryptoprocessor, a set of platform configuration registers; receiving, from the cryptoprocessor, the set of platform configuration registers; and sending a response to the integrity verifier, the response including the new nonce and the set of platform configuration registers to verify a security status of the trusted platform module and the cryptoprocessor.

In one aspect, a system includes an integrity verifier; a trusted platform module; a cryptoprocessor; and a device including memory having computer-readable instructions stored therein, and one or more processors. The one or more processors are configured to execute computer-readable instructions to receive a security profile request from the integrity verifier, the request including a nonce; request, from the trusted platform module, a new nonce, wherein the new nonce is generated at least in part by the nonce and a current timestamp from a clock in the trusted platform module; receive, from the trusted platform module, the new nonce; request, from the cryptoprocessor, a set of platform configuration registers; receive, from the cryptoprocessor, the set of platform configuration registers; and send a response to the integrity verifier, the response including the new nonce and the set of platform configuration registers to verify a security status of the trusted platform module and the cryptoprocessor.

EXAMPLE EMBODIMENTS

The disclosed technology addresses the need in the art for preventing replay attacks on cryptoprocessors lacking internal clocks. Prior to describing such examples embodiments, several example configurations in which the above concepts can be deployed and utilized, will be described first.

The disclosure now turns to an initial discussion of example concepts and technologies for providing verifiable proof of integrity of network nodes traversed by packets.

A computer network can include different nodes (e.g., network devices, client devices, sensors, and any other computing devices) interconnected by communication links and segments for sending data between end nodes. Many types of networks are available, including, for example, local area networks (LANs), wide area networks (WANs), software-defined networks (SDNs), wireless networks, core networks, cloud networks, the Internet, etc. When data traffic is transmitted through one or more networks, the data traffic typically traverses a number of nodes that route the traffic from a source node to a destination node.

While having numerous nodes can increase network connectivity and performance, it also increases security risks as each node that a packet traverses introduces a risk of unauthorized data access and manipulation. For example, when a packet traverses a node, there is a security risk that is introduced which can result from the node being potentially compromised (e.g., hacked, manipulated, captured, etc.). As a result, compliance, security, and audit procedures can be implemented to verify that network users, devices, entities and their associated network traffic comply with specific business and/or security policies.

When sensitive information is transmitted through nodes in a network, such as in battlefield, banking settings, and healthcare settings, such traffic should be sent through uncompromised nodes to prevent access to, leakage of, or tampering with the data and sensitive information carried by that traffic. If an attacker gains access to a device via some exploit, previous protection and encryption approaches for network interfaces are generally ineffective at mitigating or addressing such unauthorized access and resulting damage.

Proving that network traffic complies with specific policies can involve proving in a secure way that the traffic has traversed a well-defined set of network nodes (e.g., firewalls, switches, routers, etc.) and that such network nodes have not been modified or compromised. This can help ensure that the network nodes have performed their expected or intended actions (e.g., packet processing, security or policy compliance verification, routing, etc.) on the packet and that the packet has traversed the network nodes.

Some security approaches can aim at removing any implied trust in the network used for connecting applications hosted on devices to cloud or enterprise hosted services. Moreover, some security approaches can be implemented to verify the trustworthiness (e.g., the integrity, identity, state, etc.) of the network and/or nodes traversed by packets. In some cases, certain verification checks can be implemented to validate or verify that traffic has traversed a specific set of nodes and that such nodes are trusted and uncompromised. In some examples, certain Proof-of-Transit (POT), Trusted Platform Module (TPM), attestation, or proof of integrity approaches can be implemented to verify or validate the trustworthiness of a node in a network.

POT can enable a network user or entity to verify whether traffic traversed a defined set of network nodes. Attestation, as further described below, can also be used to verify the integrity of a node. In some cases, the approaches herein can integrate both to offer a secure approach that allows network users or entities to verify that traffic has traversed a defined set of nodes and that such nodes have not been compromised.

In some cases, TPM can be implemented to collect and report the identity of hardware and software components in a platform to establish trust for that platform. A TPM used in a computing system can report on the hardware and software of the system in a manner that allows verification of expected behavior associated with that system and, from such expected behavior, establishment of trust. The TPM can be a system component containing state that is separate from the host system on which the TPM reports identity and/or other information. TPMs can be implemented on physical resources (indirectly or directly) of the host system. In some examples, a TPM component can have a processor and memory such as RAM, ROM and/or flash memory. In other implementations of a TPM, a host processor can run TPM code while the processor is in a particular execution mode. Parts of system memory can be partitioned by hardware to ensure that memory used by the TPM is not accessible by the host processor unless the host processor is in the particular execution mode.

In some cases, trusted computing (TC) implementations, such as TPM, can rely on Roots of Trust. Roots of Trust can be system elements that should be trustworthy because misbehavior by such system elements may not be detectable. A set of roots can provide a minimum functionality that can sufficiently describe characteristics that affect a platform's trustworthiness. In some cases, determining if a Root of Trust is behaving properly may not be possible; however, it may be possible to determine how roots are implemented. For example, certificates can provide assurances that the root has been implemented in a way that renders it trustworthy.

To illustrate, a certificate may identify the manufacturer and evaluated assurance level (EAL) of a TPM. Such certification can provide a level of confidence in the Roots of Trust used in the TPM. Moreover, a certificate from a platform manufacturer may provide assurance that the TPM was properly installed on a system that is compliant with specific requirements so the Root of Trust provided by the platform may be trusted. Some implementations can rely on three Roots of Trust in a trusted platform, including Root of Trust for Measurement (RTM), Root of Trust for Storage (RTS), and Root of Trust for Reporting (RTR).

The RTM can send integrity information, such as integrity measurements, to the RTS. Generally, the RTM can be a processor controlled by a Core Root of Trust for Measurement (CRTM). The CRTM is the first set of instructions executed when a new chain of trust is established. When a system is reset, the processor (e.g., RTM) can execute the CRTM, which can then send values that indicate its identity to the RTS. Thus, in some cases, the starting point for a chain of trust can be established in this manner.

As previously noted, the TPM memory can be shielded from access by an entity other than the TPM. Since the TPM can be trusted to prevent unauthorized access to its memory, the TPM can act as an RTS. Moreover, the RTR can report on the contents of the RTS. An RTR report can be a digitally signed digest of the contents of one or more values in a TPM.

Attestation is another example trusted computing approach that can be used to verify the integrity of a node. Attestation can be applied to a node, such as a router or switch, to review logs from connected devices, such as Layer 1 (L1) or Layer (L2) connected devices and maintain these logs in trusted storage. These logs can be protected by embedding a private key into every trust anchor produced for a hardware device and publishing the device's public key as a certificate to adjacent devices. This peering device can then push log updates from trusted storage periodically and/or on some log entry event. Reviewing any provided signed logs can provide an understanding of the current trustable state of a peer device. Moreover, by looking back at the set of transactions which have occurred since boot time, a determination can be made regarding the trustworthiness of the information which that peer device is asserting.

In some examples, metadata elements containing security measurements or evidence, can be used to provide verifiable evidence of device trustworthiness (e.g., integrity, state, etc.). The metadata elements can include applicable data for verifying trustworthiness of a device and be provided through an applicable technique for verifying device trustworthiness. For example, the metadata elements can be provided as part of a canary stamp associated with the device. A canary stamp can indicate or otherwise include a signed measurement associated with a device for verifying trustworthiness of the device. In turn, such measurements can be referred to as canary stamps because each signed measurement is like a stamp proving its authenticity, and like a canary in a coal mine that indicates an early sign of trouble. Such verifiable evidence can be appended or included in packets transmitted by nodes on a network. The metadata elements can thus be used to evaluate the trustworthiness of a node(s) and react accordingly. For example, a device or entity can review metadata elements associated with a node to determine that the node should not be trusted and adjust a network policy to mitigate possible damage.

In some implementations, dedicated cryptoprocessors, such as a processor in TPM platform, can take measurements to attest to the trustworthiness (e.g., identity, integrity, etc.) of a node and its environment (e.g., software, hardware, operating system, running binaries, firmware, etc.). These measurements include evidence that the node is in a safe state. In some cases, these measurements can be provided through canary stamps, as previously described. However, a receiver of such evidence should be able to certify that the evidence is fresh, as the evidence can become stale thereby potentially reducing its effectiveness in reflecting the current trustworthiness of a node. For example, without ensuring freshness of such evidence, an attacker has an opening to inject previously recorded measurements and asserting what is replayed as being current.

Some approaches can detect the replaying of old evidence via a “nonce”. A nonce is an arbitrary number that can be used to introduce randomness. In some instances, a nonce can be used just once in a cryptographic communication. Further, a nonce can be passed into a TPM and/or incorporated into a canary stamp/metadata. In some cases, a result provided by the TPM can include a signature based on the nonce. Since the nonce can be grounded in a transactional challenge/response interaction model, in some cases the nonce may be less effective with unidirectional communications originating from an attesting device. For example, a nonce may less effective with an asynchronous push, multicast, or broadcast message.

However, there are numerous use cases where a platform assessing whether its peers are trustworthy is advantageous. Being able to perform a unidirectional attestation using an asynchronous push, multicast, or broadcast message in conjunction with trusted binaries opens many possibilities for platforms to assess whether their peers are trustworthy. Detection of invalid attestations can trigger alarms or events, reduction of network access from a suspect device, or can become a part of Admission Control (e.g., IEEE 802.1X). Some platforms can be configured to support the unidirectional attestation mechanism.

Other freshness approaches can be based on trusted computing capabilities, such as TPM. For example, a token can be generated which allows external entities to validate freshness of asserted data based on the state of internal counters within the TPM. This token can be used to detect replay attacks, and provide attestation for asynchronous push, multicast, and broadcast messages.

Various of the foregoing approaches can be combined with TPM-integrated capabilities aimed at verifying that valid compute components, such as binary processes, are running on a node. These capabilities can include, for example, Trusted Execution Environments (TEE) which provide runtime malware protections, Authenticated Code Modules (ACM) which ensure that only digitally-signed code modules can be loaded into a processor, and the like. These technologies can validate that a processor is running known software with a valid chain of binary signatures.

In some cases, metadata elements, e.g. canary stamps, and tokens can be created by extracting current counters (e.g., clock, reset, restart) from a node's TPM, and incorporating such counters and security measures taken from the node into a packet. In some examples, the current counters and/or security measures can be hashed with information within an external TPM. The metadata elements and tokens can thereby provide a non-spoofable token or metadata element, which can bind continuously incrementing counters on an attestee with a known external state. Any resetting of the TPM counters is visible in any subsequent TPM queries, and any restarting of a platform is also exposed in subsequent TPM queries. Within these bounds of reset and restart, the TPM's time ticks counter continuously increments. Therefore, any push of attestee TPM information which includes these counters can be determined to have occurred subsequent to any previously-received measurement. Also, if the reset and restart counters have not changed, the incremental time since any previous measurement can also be known.

In some cases, a large amount of information that should be trusted by network peers may not be contained within the TPM's Platform Configuration Register (PCR). As a result, indirect methods of validating that a node has not been compromised can be applied.

The receipt of the metadata elements, e.g. canary stamps, and/or tokens can mean that a receiver should have the option of verifying the information. In many cases, such verification can be performed without the need of supplementary evidence being sent with the canary stamp. Moreover, in non-controller based or centralized implementations, the verification steps do not have to occur at the receiver.

In some integrity verification implementations, a controller or device can implement an integrity verification application. The integrity verification application can be designed to recognize change events and evaluate known good values, which allow evaluation of a boot-integrity stamp and a running process binary signature stamp based on, for example, TPM counters, timestamps, nonces, and/or time tokens. On any discrepancy, a controller or centralized device can isolate a compromised node from its network peers by shutting down the interfaces of the node.

In some examples, the metadata elements, e.g. canary stamps, and/or verifications for integrity can be implemented, such as a measured-boot stamp (e.g., SHA1 hash over PCRs 0-7), a verified-boot stamp (e.g., which can verify that only recognized binaries were executed when booting), a process-stamp (e.g., root-of-trust validated through a process which is asserting a particular protocol or protocols), a file-system stamp (e.g., all files within a vendor determined set of directories), a log-integrity stamp (e.g., used to augment existing integrity analytics and forensics), a configuration stamp (e.g., State of the current device configuration), etc. Some implementations can achieve all or some of these stamps, depending on the implementation. Moreover, in some implementations, all or some of these stamps can be implemented or achieved using a single or multiple stamps.

As previously explained, TPM provides methods for collecting and reporting the identity of hardware and software components in a platform to establish trust for that platform. TPM functionality can be embedded in a variety of devices including mobile phones, personal computers, network nodes (e.g., switches, routers, firewalls, servers, network appliances, etc.), and/or any other computing devices. Further, attestation can describe how the TPM can be used as a hardware root of trust and offer proof of integrity of a node. Such integrity can include hardware integrity, software integrity (e.g., micro loader, firmware, boot loader, kernel, operating system, binaries, files, etc.), and runtime integrity.

In some cases, TPM and attestation can be implemented as described herein to provide proof of integrity and proof of transit through uncompromised nodes. In some examples, metadata elements and tokens containing or reflecting security measures are used as previously mentioned to validate the integrity of a node and perform continuous evaluation of node integrity. Thus, the metadata elements and tokens described herein can be used to provide proof of transit through uncompromised nodes.

In some examples, the metadata elements and tokens can be added as additional metadata to packets that traverse a network where proof of transit via uncompromised nodes is desired. Various strategies can be implemented for transporting the metadata elements and tokens in a packet. In some cases, the metadata elements and tokens can be carried within an In-Situ (or in-band) Operations, Administration and Management (IOAM) data field.

In some implementations, the metadata elements and tokens can be carried with IOAM trace data. For example, a canary stamp can be carried as part of an IOAM data field in a variety of encapsulation protocols such as, for example and without limitation, IPv4, IPv6, NSH (Network Service Header), etc. In some cases, the canary stamp can be carried in an IOAM data field as an IOAM Trace option data element (e.g., with an IOAM Trace type for node integrity canary stamp). A metadata element, token, or digest, e.g. canary stamp digest, can be added in the IOAM trace option of a packet by each node that forwards the packet.

When the packet reaches a node (e.g., the destination node and/or an intermediate node) that removes IOAM metadata (e.g., an IOAM decapsulating node), the validity of the metadata element and/or token in the packet can be verified to determine that the packet traversed uncompromised nodes. In some examples, since canary stamps are time bound, the packet trace timestamps defined in IOAM can be used to validate the canary stamp in the time window the packet traversed that node.

Verification can be performed without placing a large transactional load on the verifier or a device, such as a controller, that will ultimately validate the security measurements associated with the metadata elements or tokens. This is because the measurement values can often change infrequently. The verifier may only need to validate a metadata element and/or token carried within an IOAM data trace whenever the associated security measurements associated change (e.g., a verifier may only need to check with a controller whenever it sees a node's TPM extends a PCR value which was not previously confirmed by the verifier).

In some cases, when only the time ticks within a signed metadata element increases, only the signature of the metadata element is validated. To do this, the verifier may use the public key of any node which can place a metadata element. Such signature validation can be done without using a controller to verify the measurements.

In another example, a packet can carry IOAM POT data with space optimization of metadata element values, e.g. canary stamp values. For example, a new IOAM POT data field can carry a canary stamp or a hash extend of a canary stamp and, in turn, canary stamp data can be carried across nodes. In some cases, a canary stamp hash extend can be a similar method as PCR extend operation performed by TPMs.

In some cases, the canary stamp hash can provide a one-way hash so that a canary stamp recorded by any node cannot be removed or modified without detection. IOAM proof of transit option data for a canary stamp digest can be defined by a hash algorithm (e.g., 20 octets with SHA1, 32 octets with SHA 256, etc.). In some implementations, each node along a path of the packet can forward the packet with a new or updated canary stamp digest. In some examples, the new or updated canary stamp digest can be generated by a node as follows: IOAM canary stamp digest new value=Digest of (IOAM canary stamp digest old value∥ hash (canary stamp of the node)), where the IOAM canary stamp digest old value can refer to the canary stamp digest included in the packet by one or more previous hops.

Moreover, in some cases, a Per Packet Nonce (PPN), where PPN changes per packet and is carried as another field within the IOAM metadata option, can be added to provide robustness against replay attacks. To illustrate, in some examples, a PPN can be added as follows: IOAM canary stamp digest new value=Digest of (IOAM canary stamp digest old value∥hash(canary stamp of the node∥PPN)). A node creating the new value for the IOAM canary stamp digest can thus take the value of any previous IOAM canary stamp digest and extend/hash that value with the node's current canary stamp. The result of the concatenation and hashing can then be written into IOAM POT data (or other IOAM data fields) as the new IOAM canary stamp digest.

At the verifier (e.g., the device verifying the canary stamp data), the same operation can be performed over expected canary stamp values calculated for the nodes that are traversed in the time window when the packet was forwarded. A verifier can be an inline device or a centralized device. Moreover, in some examples, nodes that are expected to be traversed can be identified using IOAM tracing, routing state or by sending active probes. A match between the value of POT data carrying specific metadata elements, e.g. a canary stamp digest and the expected canary stamp value, can prove that the packet traversed through trusted or uncompromised nodes.

In some examples, one or more strategies can be implemented to optimize metadata element validation. For example, metadata elements, e.g. canary stamps, can detect attempts of a replay attack by embedding a nonce as well as TPM or TPM2 counters (e.g., clock, reset, restart). In some cases, this nonce can be part of the metadata elements and different from the PPN described above.

The nonce is relevant to a receiver as the interval from the nonce's creation time to the first stamp received by the verifier can define the interval of freshness (e.g., the measurement is no older than this interval of freshness). From there, the TPM2 time ticks counter can be used to maintain that initial gap of freshness even without the delivery of a new nonce.

In some implementations, to optimize metadata element or token validation across nodes, the following approaches can be implemented to deliver synchronization information from a central component to each node and the verifier. For example, a central server can broadcast or multicast centralized nonce values (e.g., tracked random numbers). Each node can pick up the latest nonce and use it to attest a value. A verifier can know the freshness of a metadata element or token it receives from each node. This freshness can be the delta in time since that particular nonce was issued. Subsequent attestations can use the incrementing time ticks to prove freshness from that initial time gap. In some cases, the issuing of new nonces can reset the time gap to a potentially shorter interval.

Moreover, in some cases, each node can embed attested time within its metadata element. To get attested time, a TUDA (Time-Based Uni-Directional Attestation) scheme such as the TUDA scheme described in tools.ietforg/id/draft-birkholz-i2nsf-tuda-01.html, the contents of which are incorporated herein by reference in their entirety, can be used. This can result in the availability of both the attested time at a node, as well as the value of the TPM2 counters at this node when a TUDA time-synchronization token was created. This can eliminate the use of a central nonce authority, but can increase the size of the metadata element as the nonce can be replaced by the TUDA time-synchronization token. This approach may also implement a central timestamp authority as per TUDA. In some examples, for each hop, a canary stamp digest value can be: IOAM canary stamp digest new value=Digest of (IOAM canary stamp digest old value∥hash(canary stamp of the node∥TUDA time-synchronization token of the node)).

The attestation routing orchestrator 104 can direct, to the particular candidate next-hop node, a data packet destined for the destination node. For example, in some cases, the attestation routing orchestrator 104 can provide attested route information (e.g., validated canary stamp data, security measurements, etc.) to an attested route manager 402D of the source node 402 in order to facilitate the source node 402 sending the data packet to the particular candidate next-hop node. The attested route information can be indicative of the trustworthiness of each of the candidate next-hop nodes 108A-N.

This approach can provide numerous benefits. For example and without limitation, with this approach, a verifier can limit the number of verifications by verifying the signature of a hop's time-synchronization token only when it changes. Moreover, with this approach, there may not be a time gap nonce changeover freshness when a first measurement is received. Further, in some cases, this approach can be implemented without also carrying a PPN or without synchronizing a nonce across nodes as previously described.

Further, an attestor, e.g. a node or a verifier, can use random numbers, otherwise pseudo-random numbers, created by peers and/or the attestor to generate and verify attestation information. Specifically, the attestor can accumulate random numbers from one or more layer 2 peers. The random numbers can be accumulated from the peers over a specific amount of time, e.g. a short duration of time. In turn, the random numbers can be combined into a number through an applicable technique, e.g. a Bloom filter. This number can serve as a nonce for a cryptoprocessor for generating a result. As follows, the layer 2 peers, potentially including the attestor, can use the result created by the cryptoprocessor, to verify/validate that their corresponding provided random number was used in generating the nonce ultimately used by the cryptoprocessor to create the result. In turn, the layer 2 peers, potentially including the attestor, can generate verified attestation information based on the random numbers generated by the peers, the nonce created from the random numbers, and/or the result created by the cryptoprocessor from the nonce.

Having provided an initial discussion of example concepts and technologies for providing explicit verifiable proof of integrity of network nodes traversed by packets, the disclosure now turns to FIG. 1 .

FIG. 1 is a block diagram of an example of networking environment 100 in accordance with some implementations. While pertinent features are shown, those of ordinary skill in the art will appreciate from the present disclosure that various other features have not been illustrated for the sake of brevity and so as not to obscure aspects of the example implementations disclosed herein.

In this example, the networking environment 100 can include a network 114 of interconnected nodes (e.g., 108A-N, 110A-N, and 112A-N). The network 114 can include a private network, such as a local area network (LAN), and/or a public network, such as a cloud network, a core network, and the like. In some implementations, the network 114 can also include one or more sub-networks, such as sub-network 114A. Sub-network 114A can include, for example and without limitation, a LAN, a virtual local area network (VLAN), a datacenter, a cloud network, a wide area network (WAN), etc. In some examples, the sub-network 114A can include a WAN, such as the Internet. In other examples, the sub-network 114A can include a combination of nodes included within a LAN, VLAN, and/or WAN.

The networking environment 100 can include a source node 102. The source node 102 can be a networking device (e.g., switch, router, gateway, endpoint, etc.) associated with a data packet that is destined for a destination node 116. The source node 102 can communicate with candidate next-hop nodes 108A-N on the network 114. Each of the candidate next-hop nodes 108A-N can be included within a respective route between the source node 102 and the destination node 116. Moreover, in some cases, each of the candidate next-hop nodes 108A-N can communicate with candidate second hop nodes 110A-N in the network 114. Each of the candidate second hop nodes 110A-N can similarly communicate with candidate N-hop nodes 112A-N in the network 114.

The networking environment 100 can also include an attestation routing orchestrator 104. The attestation routing orchestrator 104 can communicate with the candidate next-hop nodes 108A-N. In some implementations, the attestation routing orchestrator 104 can obtain attestation data (e.g., canary stamps, security measures, signatures, and/or metadata) or vectors from the candidate next-hop nodes 108A-N. In some examples, the attestation routing orchestrator 104 can obtain additional information from candidate second-hop nodes 110A-N and/or candidate N-hop nodes 112A-N and utilize the additional information in selecting a particular candidate next-hop node for a packet. In some implementations, the attestation routing orchestrator 104 can also obtain additional information from nodes that are more than two hops away (e.g., candidate third hop nodes, candidate fourth hop nodes, etc.).

The attestation routing orchestrator 104 can communicate with a verifier system 106. While, the verifier system 106 is conceptually shown as being implemented separate from the network 114, the verifier system 106 can be implemented within the network 114, e.g. as part of a network device in the network 114. In some implementations, the attestation routing orchestrator 104 can obtain trusted state, such as a trusted image vector, from the verifier system 106. The verifier system 106 can include a verified state repository 106A and one or more servers 106B. In some examples, the verified state in the verified state repository 106A can include one or more verified images, verified security measurements, verified settings, verified node data, and/or any other verified trust or integrity data. In some implementations, the verified state in the verified state repository 106A can include one or more trusted states or image vectors that are known with a degree of confidence to represent uncompromised states or images (e.g., states or images that have not been hacked, attacked, improperly accessed, etc.).

As will be described in great detail with reference to FIG. 4 , in some cases, the attestation routing orchestrator 104 can select and direct a data packet to a particular candidate next-hop node of the candidate next-hop nodes 108A-N based on a trusted state or image vector and the attestation states or vectors. Moreover, the attestation routing orchestrator 104 can direct the data packet destined for the destination node 116 to the particular candidate next-hop node.

FIG. 2 is a block diagram of another example networking environment 200 in accordance with some implementations. In this example, the networking environment 200 includes a source node 202 that implements an attestation routing orchestrator 202A. In some implementations, the attestation routing orchestrator 202A can be similar to, or adapted from, the attestation routing orchestrator 104 in FIG. 1 .

The source node 202 can include one or more processors 202B. In some implementations, the one or more processors 202B can provide processing resources for generating a confidence scores for the candidate next-hop nodes 108A-N. In some implementations, the one or more processors 202B can provide processing resources for selecting a particular confidence score, from the confidence scores, that satisfies one or more selection criteria.

In some examples, the source node 202 can include a memory 202C. The memory 202C can be, for example and without limitation, a non-transitory memory, such as RAM (random-access memory), ROM (Read-only memory), etc. The memory 202C can store the data, such as the packet destined for the destination node 116. In some implementations, the memory 202C can store a trusted state or image vector obtained from the verifier system 106. In some implementations, the memory 202C can store attestation states or vectors obtained from the candidate next-hop nodes 108A-N and optionally attestation states or vectors obtained from the candidate second hop nodes 110A-N and/or the candidate N-hop nodes 112A-N. The source node 202 can also include a network interface 202D for obtaining, receiving, and transmitting the data packets and states or vectors.

In some implementations, the source node 202 can select and direct a data packet to a particular candidate next-hop node based a trusted state or image vector and the attestation states or vectors.

FIG. 3 is a block diagram of another example networking environment 300 in accordance with some implementations. In this example, one or more of the candidate next-hop nodes 108A-N can relay a trusted state or image vector from the verifier system 106 to the source node 302. In some implementations, the attestation routing orchestrator 302A can be similar to, or adapted from, the attestation routing orchestrator 104 in FIG. 1 and/or the attestation routing orchestrator 202A in FIG. 2 .

In some implementations, the verifier system 106 can sign the trusted state or image vector and provide the signed trusted state or image vector to a particular candidate next hop node, which in turn can provide the signed trusted state or image vector to the source node 302. In some implementations, having the particular candidate next hop node provide the signed trusted state or image vector can reduce attestation time (e.g., the time to determine trustworthiness of the particular candidate next hop node) because the source node 302 may not need to contact a remote node (verifier system 106). In some implementations, attestation time can be further reduced because a single attestation process (e.g., the verifier system 106 signing the trusted state or image vector) facilitates the attesting of multiple source nodes. In other words, trusted states or image vectors may not be generated and evaluated on a per source node basis.

Moreover, in implementations in which the source node 302 is not connected to the verifier system 106 (e.g., link down), obtaining the trusted state or image vector from the particular candidate next hop provides an alternative mechanism for node attestation. In some implementations, the verifier system 106 appends a time-stamped response to the trusted state or image vector as part of the signing process, which can be referred to as stapling. Consequently, the source node 302 may not contact the verifier system 106 in order to attest a particular candidate next hop node.

FIG. 4 is a block diagram of an example controller-orchestrated attestation-based routing 400, in accordance with some implementations. In some examples, the source node 402 is similar to, or adapted from, the source node 102 in FIG. 1 . As illustrated in FIG. 4 , the attestation routing orchestrator 104 is separate from, but coupled (e.g., connected) to, the source node 402. In some examples, the attestation routing orchestrator 104 can include a controller with knowledge of the network 114 that includes the candidate next-hop nodes 108A-N and optionally the candidate second-hop nodes 110A-N and/or the candidate N-hop nodes 112A-N.

For example, in some implementations, the attestation routing orchestrator 104 can be a network management system (NMS). As another example, in some implementations, the attestation routing orchestrator 104 can be an intent-based networking system, such as Cisco's Digital Network Architecture (DNA). As yet another example, in some implementations, the attestation routing orchestrator 104 can be a wireless LAN controller (WLC), and the candidate next-hop nodes 108A-N and optionally the candidate second hop nodes 110A-N and/or the candidate N-hop nodes 112A-N can be networking devices such as access points, user devices, switches, routers, firewalls, etc.

The attestation routing orchestrator 104 can obtain attestation data (e.g., canary stamps) from the candidate next-hop nodes 108A-N. Each of the candidate next-hop nodes 108A-N can be included within a respective route between the source node 402 and a destination node (e.g., 114). In some implementations, the respective routes are independent of each other.

The attestation routing orchestrator 104 can determine confidence scores based on the attestation data. For example, in some cases, each of the confidence scores can be based on a comparison between a corresponding one of the attestation data and a trusted state or image vector. In some implementations, the attestation routing orchestrator 104 can obtain the trusted state or image vector from the verifier system 106.

In some examples, the attestation routing orchestrator 104 can obtain attestation data from candidate second-hop nodes (e.g., 110A-N) and/or candidate N-hop nodes (112A-N). Each of the candidate second-hop nodes and/or the candidate N-hop nodes can be included within a respective route between a corresponding one of the candidate next-hop nodes 108A-N and the destination node. Moreover, each of the confidence scores can additionally be based on a comparison between a corresponding one of the attention data and the trusted state or image vector in combination with a comparison between another corresponding one of the attestation data from the candidate next-hop nodes 108A-N and the trusted state or image vector.

The attestation routing orchestrator 104 can select, from the confidence scores, a particular confidence score that satisfies one or more selection criteria. The particular confidence score is associated with a particular candidate next-hop node of the candidate next-hop nodes 108A-N.

The attestation routing orchestrator 104 can directs, to the particular candidate next-hop node, a data packet destined for the destination node. For example, in some cases, the attestation routing orchestrator 104 can provide attested route information (e.g., validated canary stamp data, security measurements, etc.) to an attested route manager 402D of the source node 402 in order to facilitate the source node 402 sending the data packet to the particular candidate next-hop node. The attested route information can be indicative of the trustworthiness of each of the candidate next-hop nodes 108A-N.

For example, in some implementations, the attested route information includes an identifier (e.g., an IP address, a MAC address, an SSID, etc.) identifying a secure candidate next-hop node of the candidate next-hop nodes 108A-N. In this example, the source node 402 can provide the data packet based on the identifier in order to route the data packet to the secure, particular candidate next-hop node.

As another example, in some implementations, the attested route information can include confidence scores associated with the candidate next-hop nodes 108A-N. In this example, the attested route manager 402D can select a particular candidate score based on one or more selection criteria. Moreover, the attested route manager 402D can provide the data packet to the particular next-hop node associated with the particular candidate score. In some examples, the attestation routing orchestrator 104 can cease to direct additional data packets to the particular candidate next-hop node in response to determining that the particular confidence score falls below a confidence threshold.

In some cases, the source node 402 can include one or more processors 402A. The one or more processors 402A can provide processing resources for managing attested route information obtained from the attestation routing orchestrator 104. The source node 402 can also include a memory 402B. The memory 402B can include, for example, a non-transitory memory such as RAM, ROM, etc. In some examples, the memory 402B can store data such as the obtained attested route information and data packets to be transmitted. The source node 402 can also include a network interface 402C for obtaining the attested route information and sending/receiving other data.

In some cases, whether a network device has been compromised can be determined based on indicators associated with the network device and time information. The indicators can include, but are not limited to, a set of security measurements or evidence footprints which indicate whether a particular device is compromised. Such indicators can come from one or more sources such as, for example and without limitation, TPM, canary stamps, Syslog, YANG Push, EEM, peer devices, traffic counters, and other sources. Visibility can be a method of identifying a compromise in a timely manner.

The disclosure now turns to FIGS. 5 and 6 , which illustrate example systems and methods for implementing aspects of the present technology.

Modular devices or devices with multiple hardware roots of trust pose particular challenges for security assessment. The presence of multiple hardware roots of trust means that all must be verified independently to ensure that no portion of the overall device has been compromised. Modular devices pose an even greater challenge, where portions of the device may be replaced but security assessments must last the lifetime of the deployed device.

The present technology solves a need in the art for secure verification of devices whose cryptoprocessors (e.g., multiple hardware roots) lack internal clocks. Using a clock in a trusted platform module and entangling a current timestamp with a nonce, a new nonce can be used to prevent replay attacks on such cryptoprocessors. FIGS. 5 and 6 detail a system and method, respectively, for this technology.

FIG. 5 illustrates an example system in accordance with some aspects of the present technology. Upon receiving a request for a security profile for a cryptoprocessor 530 lacking an internal clock, an internal processing component 510 can forward a nonce to a trusted platform module 520, which can create a new nonce from the nonce and a current timestamp. This can be used as a seed to evaluate the integrity of cryptoprocessor 530, which lacks an internal clock.

Integrity verifier 500 serves as an independent device which can obtain and assess the security profile of cryptoprocessor 530. To obtain this security profile, integrity verifier 500 can send a nonce (random number) to internal processing component 510 (operation 5.1). Integrity verifier 500 can hold public keys corresponding to private keys held by virtual trusted platform module 520 and cryptoprocessor 530, and use these public keys to validate digital signatures.

Internal processing component 510 serves as an intermediary between integrity verifier 500 and virtual trusted platform module 520 and cryptoprocessor 530. Virtual trusted platform module 520 and cryptoprocessor 530 exist in a hardware root-of-trust. Internal processing component 510 can send the nonce to virtual trusted platform module 520 for modification with a current timestamp (operations 5.2 and 5.3).

In order for secure modification of the nonce to take place, certain conditions are assumed. First, any information used to update the nonce is unchangeable. This is avoided by the presence of virtual trusted processor module 520 in a hardware root-of-trust or secure enclave. Second, the information used to update the nonce is unpredicted ahead of time. This is solved by using a current timestamp to modify the nonce. Third, the algorithm used to generate the new nonce has a unique solution given the original nonce (the function is injective).

Internal processing component 510 can send the new nonce, a function of the original nonce and the current timestamp, to cryptoprocessor 530, which uses this nonce to generate and respond with a set of current platform configuration registers (operations 5.4 and 5.5). In some example embodiments, these transmissions will pass over a hop switch in a network, wherein the internal processing component 510 or virtual trusted platform module 520 exist on hop switches sitting at least one hop away from cryptoprocessor 530. This set-up can allow for a split-device retrieval of security posture, and also allow these hop switches to act as subscribable entities for changing security postures which have been measured for integrity verifier 500. The security posture of devices could be further used to allow or disallow communications to cryptoprocessor 530.

Internal processing component 510 can send these platform configuration registers and the new nonce back to integrity verifier 500 (operation 5.6). Both the platform configuration registers and the new nonce are digitally signed with a private key by cryptoprocessor 530 and virtual trusted platform module 520, respectively. Integrity verifier 500 can use corresponding public keys to validate these signatures.

Without distributing another nonce from integrity verifier 500 to internal processing component 510, the process can be repeated and yield updated platform configuration registers (operations 5.7, 5.8, 5.9, 5.10, and 5.11). This is because a new timestamp is used to update the original nonce by virtual trusted platform module 520, and that timestamp changes with time.

In some embodiments, internal processing component 510 will not receive responses from virtual trusted platform module 520 or cryptoprocessor 530 without validating its own security status to these devices, which may include recent security reports, behavior analysis of the device, or other factors. This can be done by sharing internal measurements, through a third party verifier such as integrity verifier 500, or by other means. For example, a trustworthiness level of a device, assigned by a verifier like integrity verifier 500, could be boot-verified, unverified, or compromised, depending on the state of the device. Communications could proceed or halt depending on a device's status.

FIG. 6 illustrates an example method in accordance with some aspects of the present technology. FIG. 6 will be described from the perspective of internal processing component 510 of FIG. 5 . However, it should be understood that internal processing component 510 is implemented by one or more processors configured to execute computer-readable instructions stored on one or more associated memories to perform the steps of FIG. 6 , described below.

At process 600, internal processing component 510 receives a security profile request from an integrity verifier 500. The security profile requests includes a nonce which is used as a seed for retrieving the security profile from a cryptoprocessor 530. The security profile itself will include measurements from cryptoprocessor 530 such as integrity measurements, peak cell rate values, or other measures of security.

At process 610, internal processing component 510 requests a new nonce from virtual trusted platform module 520, and receives this new nonce at process 620. The new nonce is a function of the original nonce and a current timestamp. In some embodiments, virtual trusted platform module 520 can use the original nonce as a seed for an internal random number generator, wherein the internal random number generates the new nonce. By modifying the nonce with a timestamp, the system can prevent replay attacks that cryptoprocessor 530, lacking an internal clock, would otherwise be vulnerable to.

At process 630, internal processing component 510 requests a set of platform configuration registers from cryptoprocessor 530, and receives these platform configuration registers at process 640. The platform configuration registers can include integrity measurements, peak cell rate values, or other measures of cryptoprocessor 640.

At process 650, internal processing component 510 sends the set of platform configuration registers and the new nonce to integrity verifier 500. The new nonce allows integrity verifier 500 to ensure that a replay attack has not occurred, which could not be guaranteed with the original nonce. Furthermore, the information received by integrity verifier 500 can be signed with private keys, and integrity verifier 500 can confirm these signatures using the corresponding public keys.

The disclosure now turns to FIGS. 7 and 8 , which illustrate example network nodes and computing devices, such as switches, routers, client devices, endpoints, servers, and so forth.

FIG. 7 illustrates an example network device 700 suitable for performing switching, routing, and other networking operations. Network device 700 includes a central processing unit (CPU) 704, interfaces 702, and a connection 710 (e.g., a PCI bus). When acting under the control of appropriate software or firmware, the CPU 704 is responsible for executing packet management, error detection, and/or routing functions. The CPU 704 can accomplish these functions under the control of software including an operating system and any appropriate applications software. CPU 704 may include one or more processors 708, such as a processor from the INTEL X86 family of microprocessors. In some cases, processor 708 can be specially designed hardware for controlling the operations of network device 700. In some cases, a memory 706 (e.g., non-volatile RAM, ROM, etc.) also forms part of CPU 704. However, there are many different ways in which memory could be coupled to the system.

The interfaces 702 are typically provided as modular interface cards (sometimes referred to as “line cards”). Generally, they control the sending and receiving of data packets over the network and sometimes support other peripherals used with the network device 700. Among the interfaces that may be provided are Ethernet interfaces, frame relay interfaces, cable interfaces, DSL interfaces, token ring interfaces, and the like. In addition, various very high-speed interfaces may be provided such as fast token ring interfaces, wireless interfaces, Ethernet interfaces, Gigabit Ethernet interfaces, ATM interfaces, HSSI interfaces, POS interfaces, FDDI interfaces, WIFI interfaces, 3G/4G/5G cellular interfaces, CAN BUS, LoRA, and the like. Generally, these interfaces may include ports appropriate for communication with the appropriate media. In some cases, they may also include an independent processor and, in some instances, volatile RAM. The independent processors may control such communications intensive tasks as packet switching, media control, signal processing, crypto processing, and management. By providing separate processors for the communications intensive tasks, these interfaces allow the master microprocessor 704 to efficiently perform routing computations, network diagnostics, security functions, etc.

Although the system shown in FIG. 7 is one specific network device of the present technologies, it is by no means the only network device architecture on which the present technologies can be implemented. For example, an architecture having a single processor that handles communications as well as routing computations, etc., is often used. Further, other types of interfaces and media could also be used with the network device 700.

Regardless of the network device's configuration, it may employ one or more memories or memory modules (including memory 706) configured to store program instructions for the general-purpose network operations and mechanisms for roaming, route optimization and routing functions described herein. The program instructions may control the operation of an operating system and/or one or more applications, for example. The memory or memories may also be configured to store tables such as mobility binding, registration, and association tables, etc. Memory 706 could also hold various software containers and virtualized execution environments and data.

The network device 700 can also include an application-specific integrated circuit (ASIC) 712, which can be configured to perform routing and/or switching operations. The ASIC 712 can communicate with other components in the network device 700 via the connection 710, to exchange data and signals and coordinate various types of operations by the network device 700, such as routing, switching, and/or data storage operations, for example.

FIG. 8 illustrates a computing system architecture 800 including various components in electrical communication with each other using a connection 806, such as a bus. Example system architecture 800 includes a processing unit (CPU or processor) 804 and a system connection 806 that couples various system components including the system memory 820, such as read only memory (ROM) 818 and random access memory (RAM) 816, to the processor 804. The system architecture 800 can include a cache 802 of high-speed memory connected directly with, in close proximity to, or integrated as part of the processor 804. The system architecture 800 can copy data from the memory 820 and/or the storage device 808 to the cache 802 for quick access by the processor 804. In this way, the cache can provide a performance boost that avoids processor 804 delays while waiting for data. These and other modules can control or be configured to control the processor 804 to perform various actions.

Other system memory 820 may be available for use as well. The memory 820 can include multiple different types of memory with different performance characteristics. The processor 804 can include any general purpose processor and a hardware or software service, such as service 1 810, service 2 812, and service 3 814 stored in storage device 808, configured to control the processor 804 as well as a special-purpose processor where software instructions are incorporated into the actual processor design. The processor 804 may be a completely self-contained computing system, containing multiple cores or processors, a bus, memory controller, cache, etc. A multi-core processor may be symmetric or asymmetric.

To enable user interaction with the computing system architecture 800, an input device 822 can represent any number of input mechanisms, such as a microphone for speech, a touch-sensitive screen for gesture or graphical input, keyboard, mouse, motion input, speech and so forth. An output device 824 can also be one or more of a number of output mechanisms known to those of skill in the art. In some instances, multimodal systems can enable a user to provide multiple types of input to communicate with the computing system architecture 800. The communications interface 826 can generally govern and manage the user input and system output. There is no restriction on operating on any particular hardware arrangement and therefore the basic features here may easily be substituted for improved hardware or firmware arrangements as they are developed.

Storage device 808 is a non-volatile memory and can be a hard disk or other types of computer readable media which can store data that are accessible by a computer, such as magnetic cassettes, flash memory cards, solid state memory devices, digital versatile disks, cartridges, random access memories (RAMs) 816, read only memory (ROM) 818, and hybrids thereof.

The storage device 808 can include services 810, 812, 814 for controlling the processor 804. Other hardware or software modules are contemplated. The storage device 808 can be connected to the system connection 806. In one aspect, a hardware module that performs a particular function can include the software component stored in a computer-readable medium in connection with the necessary hardware components, such as the processor 804, connection 806, output device 824, and so forth, to carry out the function.

For clarity of explanation, in some instances the present technology may be presented as including individual functional blocks including functional blocks comprising devices, device components, steps or routines in a method embodied in software, or combinations of hardware and software.

In some embodiments the computer-readable storage devices, mediums, and memories can include a cable or wireless signal containing a bit stream and the like. However, when mentioned, non-transitory computer-readable storage media expressly exclude media such as energy, carrier signals, electromagnetic waves, and signals per se.

Methods according to the above-described examples can be implemented using computer-executable instructions that are stored or otherwise available from computer readable media. Such instructions can comprise, for example, instructions and data which cause or otherwise configure a general purpose computer, special purpose computer, or special purpose processing device to perform a certain function or group of functions. Portions of computer resources used can be accessible over a network. The computer executable instructions may be, for example, binaries, intermediate format instructions such as assembly language, firmware, or source code. Examples of computer-readable media that may be used to store instructions, information used, and/or information created during methods according to described examples include magnetic or optical disks, flash memory, USB devices provided with non-volatile memory, networked storage devices, and so on.

Devices implementing methods according to these disclosures can comprise hardware, firmware and/or software, and can take any of a variety of form factors. Typical examples of such form factors include laptops, smart phones, small form factor personal computers, personal digital assistants, rackmount devices, standalone devices, and so on. Functionality described herein also can be embodied in peripherals or add-in cards. Such functionality can also be implemented on a circuit board among different chips or different processes executing in a single device, by way of further example.

The instructions, media for conveying such instructions, computing resources for executing them, and other structures for supporting such computing resources are means for providing the functions described in these disclosures.

Although a variety of examples and other information was used to explain aspects within the scope of the appended claims, no limitation of the claims should be implied based on particular features or arrangements in such examples, as one of ordinary skill would be able to use these examples to derive a wide variety of implementations. Further and although some subject matter may have been described in language specific to examples of structural features and/or method steps, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to these described features or acts. For example, such functionality can be distributed differently or performed in components other than those identified herein. Rather, the described features and steps are disclosed as examples of components of systems and methods within the scope of the appended claims.

Claim language reciting “at least one of” a set indicates that one member of the set or multiple members of the set satisfy the claim. For example, claim language reciting “at least one of A and B” means A, B, or A and B. 

The invention claimed is:
 1. A method comprising: receiving a security profile request from an integrity verifier, the request including a nonce; requesting, from a trusted platform module, a new nonce, wherein the new nonce is generated at least in part by the nonce and a current timestamp from a clock in the trusted platform module; receiving, from the trusted platform module, the new nonce; requesting, from a cryptoprocessor, a set of platform configuration registers by sending the new nonce to the cryptoprocessor; receiving, from the cryptoprocessor, the set of platform configuration registers; and sending a response to the integrity verifier, the response including the new nonce and the set of platform configuration registers to verify a security status of the trusted platform module and the cryptoprocessor.
 2. The method of claim 1, wherein requesting the new nonce comprises sending the nonce to the trusted platform module.
 3. The method of claim 1, wherein the set of platform configuration registers comprises integrity measurements from the cryptoprocessor.
 4. The method of claim 1, wherein requesting the new nonce or requesting the set of platform configuration registers requires traversing at least one hop switch.
 5. The method of claim 4, wherein requesting the new nonce or requesting the set of platform configuration registers is conditional upon a corresponding security status of a device generating the requests.
 6. The method of claim 1, wherein the trusted platform module is separated from the cryptoprocessor by at least one hop switch.
 7. The method of claim 1, further comprising: requesting, from the trusted platform module, a second new nonce, wherein the second new nonce is generated at least in part by a new current timestamp from the clock in the trusted platform module and one of the nonces or the new nonce, the new current timestamp being after the current timestamp.
 8. The method of claim 1, further comprising: receiving, by the integrity verifier, a public key for the trusted platform module; receiving, by the trusted platform module, a private key corresponding to the public key; signing, by the trusted platform module with the private key, the new nonce; and verifying, by the integrity verifier with the public key, the new nonce.
 9. The method of claim 1, further comprising: receiving, by the integrity verifier, a public key for the cryptoprocessor; receiving, by the cryptoprocessor, a private key corresponding to the public key; signing, by the cryptoprocessor with the private key, the set of platform configuration registers; and verifying, by the integrity verifier with the public key, the set of platform configuration registers.
 10. A system comprising: an integrity verifier; a trusted platform module; a cryptoprocessor; and a device comprising: memory having computer-readable instructions stored therein, and one or more processors configured to execute computer-readable instructions to: receive a security profile request from the integrity verifier, the request including a nonce; request, from the trusted platform module, a new nonce, wherein the new nonce is generated at least in part by the nonce and a current timestamp from a clock in the trusted platform module; receive, from the trusted platform module, the new nonce; request, from the cryptoprocessor, a set of platform configuration registers by sending the new nonce to the cryptoprocessor; receive, from the cryptoprocessor, the set of platform configuration registers; and send a response to the integrity verifier, the response including the new nonce and the set of platform configuration registers to verify a security status of the trusted platform module and the cryptoprocessor.
 11. The system of claim 10, wherein requesting the new nonce comprises sending the nonce to the trusted platform module.
 12. The system of claim 10, wherein the set of platform configuration registers comprises integrity measurements from the cryptoprocessor.
 13. The system of claim 10, wherein requesting the new nonce or requesting the set of platform configuration registers requires traversing at least one hop switch.
 14. The system of claim 13, wherein requesting the new nonce or requesting the set of platform configuration registers is conditional upon a corresponding security status of the device.
 15. The system of claim 10, wherein the trusted platform module is separated from the cryptoprocessor by at least one hop switch.
 16. The system of claim 10, the one or more processors further configured to execute computer-readable instructions to: request, from the trusted platform module, a second new nonce, wherein the second new nonce is generated at least in part by a new current timestamp from the clock in the trusted platform module and one of the nonce or the new nonce, the new current timestamp being after the current timestamp.
 17. The system of claim 10, the one or more processors further configured to execute computer-readable instructions to: receive, by the integrity verifier, a public key for the trusted platform module; receive, by the trusted platform module, a private key corresponding to the public key; sign, by the trusted platform module with the private key, the new nonce; and verify, by the integrity verifier with the public key, the new nonce.
 18. The system of claim 10, the one or more processors further configured to execute computer-readable instructions to: receive, by the integrity verifier, a public key for the cryptoprocessor; receive, by the cryptoprocessor, a private key corresponding to the public key; sign, by the cryptoprocessor with the private key, the set of platform configuration registers; and verify, by the integrity verifier with the public key, the set of platform configuration registers. 